Welcome to Group 10's CMOS AND Project page for Dr. Braun's Winter '08 EE 307 (Section 2) class at Cal Poly, San Luis Obispo! Group 10 consists of Trevor McGuire (temcguir@calpoly.edu), Patrick Beck (pbeck@calpoly.edu) and Michael Brust (customblingbling@gmail.com). Click on the contents link below to get started.
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Summary of Findings
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Table 1: Measurement Summary for all Gates
|
|
Gate 1
|
Gate 2 |
Gate 3 |
Optimized Gate |
| tPLH [ns] |
1.74 |
1.41 |
0.61 |
3.65 |
| tPHL [ns] |
1.12 |
1.10 |
0.98 |
4.53 |
| tP [ns] |
1.43 |
1.25 |
0.80 |
4.09 |
Power [mW]
|
0.746 |
0.708 |
1.13 |
0.349 |
| Area [µm2] |
34.5 |
13.5 |
38.5 |
2.0 |
| FOM [ns∙mW∙µm2] |
36.8 |
11.95 |
34.8 |
2.86 |
|
|
Table 2: Gate 1 Area Summary
|
# of gates
|
Type |
W(μm) |
L(μm) |
# of gates x A (μm2)
|
| 8 |
PFET |
0.25 |
0.25 |
0.5 |
| 8 |
NFET |
16 |
0.25 |
32 |
| 1 |
PFET |
4 |
0.25 |
1 |
| 1 |
NFET |
4 |
0.25 |
1 |
| Total |
|
|
|
34.5μm2 |
|
Table 3: Gate 2 Area Summary
|
# of gates
|
Type |
W(μm) |
L(μm) |
# of gates x A (μm2)
|
| 8 |
PFET |
0.25 |
0.25 |
0.5 |
| 8 |
NFET |
16 |
0.25 |
8 |
| 2 |
PFET |
8 |
0.25 |
4 |
| 2 |
NFET |
2 |
0.25 |
1 |
| Total |
|
|
|
13.5 μm2 |
|
|
Table 4: Gate 3 Area Summary
|
# of gates
|
Type |
W(μm) |
L(μm) |
# of gates x A (μm2)
|
| 8 |
PFET |
0.25 |
0.25 |
0.5 |
| 8 |
NFET |
1 |
0.25 |
2 |
| 4 |
PFET |
8 |
0.25 |
8 |
| 4 |
NFET |
2 |
0.25 |
2 |
| 2 |
PFET |
4 |
0.25 |
2 |
| 2 |
NFET |
16 |
0.25 |
8 |
| 1 |
PFET |
32 |
0.25 |
8 |
| 1 |
NFET |
32 |
0.25 |
8 |
| Total |
|
|
|
38.5μm2 |
|
Table 5: Optimized Gate Area Summary
|
# of gates
|
Type |
W(μm) |
L(μm) |
# of gates x A (μm2)
|
| 11 |
PFET |
0.25 |
0.25 |
0.6875 |
| 11 |
NFET |
0.25 |
0.25 |
0.6875 |
| 1 |
PFET |
1.9 |
0.25 |
0.475 |
| 1 |
NFET |
0.6 |
0.25 |
0.15 |
| Total |
|
|
|
2 μm2 |
|
Introduction
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This page describes our analysis for three different 8-input CMOS AND Gate configurations. We analyze these gates based on propagation delay, power dissipation, and area. The product of these values forms our figure of merit (FOM).
The first gate, the large 2-level gate, shows the worst overall performance. The first stage contains very large transistors whereas the second stage contains somewhat smaller FETs. The second stage must drive the load, so this design shows serious flaws. The large first stage leads to high power dissipation, since P = I∙V and large transistors means large current. The small inverter leads to large propagation delay, since it does not conduct enough current to charge the load capacitance quickly. The large FETs mean large area, so this gate comes in last with FOM = 36.8.
The second gate, the medium 2-level gate, performs best due to a relatively small first stage and a large second stage. This means minimal wasted power in the early stages and enough current driving ability in the second stage to charge the load. This gate also has the smallest area, so it takes the lead with FOM = 13.5.
The third gate, the four-level AND, performs poorly overall, but shows very short propagation delays. The stages in this gate become progressively larger as they near the output. Although not a terrible design overall, this gate wastes far too much area and power in the first three stages. The large output inverter leads to low propagation delays, since it conducts enough current to charge the load capacitance quickly. The large area in gate 3 yields a large FOM =34.8. Interestingly, this gate does require successive sizing, since small initial stages can cause the output inverter to stay on almost constantly.
Finally, we design an optimized gate based on gate 2. This gate yields a tiny FOM = 2.86, due to its tiny area. This gate dissipates half the power that gate 2 did, has about seven times less area, and unfortunately operates over three times slower. We added two inverters to buffer the output, since this yields comparable performance for less area. The output swings rail-to-rail at 35 MHz and maintains greater than 0.25V noise margins at 100 MHz. This gate would more likely appear in mobile technology, since it dissipates very little power and fits in 2 square microns.
Analysis
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Gate 1
Power Measurements
Figure 1: Average power dissipation measurement for Gate 1
To calculate the power dissipation, we average the power dissipated over 10 clock cycles. Total gate power dissipation equals power supplied by both VDD and Vin minus the power supplied to the load. This goal function yields total power dissipated in the gate:
YatX(AVG(-W(Vdd) – W(Vin) – W(Cout1)), 200ns)
In this function W(*) denotes power dissipated by the argument. The sources Vdd and Vin supply power rather than dissipate it, so negative powers describe power from these sources.
Evaluating this goal function gives a power dissipation PAV = 0.746mW.
Speed Measurements
We define propagation delay as:
where tPLH and tPHL represent the low-to-high and high-to-low delays. [1]
Figure 2: Input (red) and output (green) voltage versus time for Gate 1 propagation delay measurements.
Low-to-high delay measures time between the output voltage midpoint and the input voltage midpoint when the output changes from the minimum to maximum value. We measure high-to-low when the output changes from the minimum to maximum value.
V(Vin1) and V(51) represent input and output voltage This goal function yields the logic swing midpoint:
(Max(V(51))+Min(V(51)))/2
*Note: This does not account for positive and negative overshoot. However, little overshoot appears in each case and they tend to cancel out each other.
This gives a mid-swing voltage at 1.2428V.
This goal function yields the low-to-high delay:
XatNthY(V(51),1.2428,19)- XatNthY(V(Vin1),1.25,19)
This gives tPLH = 1.734ns.
This goal function yields the high-to-low delay:
XatNthY(V(51),1.2428,20)- XatNthY(V(Vin1),1.25,20)
This gives tPHL = 1.120ns.
Evaluating this goal function yields the average propagation delay:
(XatNthY(V(51),1.2428,19)- XatNthY(V(Vin1),1.25,19)+ XatNthY(V(51),1.2428,20)- XatNthY(V(Vin1),1.25,20))/2
This gives a propagation delay tP = 1.427ns.
Area Calculation
We describe chip size as the sum of the individual MOSFET areas (W x L). The table below summarizes the calculation.
Table 2: Gate 1 Area Summary
|
# of gates
|
Type |
W(μm) |
L(μm) |
# of gates x A (μm2)
|
| 8 |
PFET |
0.25 |
0.25 |
0.5 |
| 8 |
NFET |
16 |
0.25 |
32 |
| 1 |
PFET |
4 |
0.25 |
1 |
| 1 |
NFET |
4 |
0.25 |
1 |
| Total |
|
|
|
34.5μm2 |
Figure of Merit
We define figure of merit as:
For this gate, the figure of merit equals:
FOM = (1.427ns) x (0.746mW) x (34.5μm2) = 36.72 ns·mW·μm2
Gate 2
Power Measurements
Figure 3: Average power dissipation measurement for Gate 2
We measure power dissipation at steady-state after at least 5 clock cycles.
Gate power dissipation equals “power from the source (VDD∙IDD)” plus “power from the input (VIN∙IIN)” minus “power out (VOUT∙IOUT)”.
Plotting “AVGX( - W(Vdd) - W(Vin) - W(Cout), 10n)” and using cursors yields an average power dissipation PAV = 0.708 mW.
* Note: The negative signs come from PSpice sign convention. This does yield correct power values.
Speed Measurements
We define propagation delay as:
where tPLH and tPHL represent the low-to-high and high-to-low delays.
Figure 4: Input and output voltage versus time for Gate 2 propagation delay measurements.
Low-to-high delay measures time between the output voltage midpoint and the input voltage midpoint when the output changes from the minimum to maximum value. We measure high-to-low when the output changes from the minimum to maximum value.
Plotting VIN and VOUT versus time and using cursors yields:
VOH = 2.50V VOL = 0V
These values allow us to measure the propagation delays:
tPLH = 1.41 ns tPHL = 1.10 ns
These measurements yield:
tP = 1.25 ns
Area Calculation
We describe chip size as the sum of the individual MOSFET areas (W x L). The table below summarizes the calculation.
Table 3: Gate 2 Area Summary
|
# of gates
|
Type |
W(μm) |
L(μm) |
# of gates x A (μm2)
|
| 8 |
PFET |
0.25 |
0.25 |
0.5 |
| 8 |
NFET |
16 |
0.25 |
8 |
| 2 |
PFET |
8 |
0.25 |
4 |
| 2 |
NFET |
2 |
0.25 |
1 |
| Total |
|
|
|
13.5 μm2 |
Noise Margins
Noise margins define the maximum disturbance a logic circuit can withstand without producing logic errors.
We define the high and low noise margins as:
Figure 5: Voltage Transfer Characteristic (VTC) for the unmodified Gate 2 (for comparison with Optimized Gate)
This plot shows the critical voltages VIL= 0.78V and VIH= 0.83V. From either this plot or fig. 4, we find VOL = 0V and VOH = 2.50V. This yields NMH = 1.67V and NML = 0.78V.
Figure of Merit
We define figure of merit as:
For this gate, the figure of merit equals:
FOM = (1.25ns) x (0.708mW) x (13.5μm2) = 11.95 ns·mW·μm2
Gate 3
Power Measurements
We measure power dissipation at steady-state after at least 5 clock cycles. Total gate power dissipation equals power supplied by VDD and VIN minus the power supplied to the load capacitance.
Plotting “AVGX( - W(Vdd) - W(Vin) - W(Cout), 10n)” and using cursors yields an average power dissipation PAV = 1.126mW.
Figure 6: Average power dissipation measurement for Gate 3
Speed Measurements
We define propagation delay as:
where tPLH and tPHL represent the low-to-high and high-to-low delays.
Low-to-high delay measures time between the output voltage midpoint and the input voltage midpoint when the output changes from the minimum to maximum value. We measure high-to-low when the output changes from the minimum to maximum value.
V(Vin1) and V(53) represent input and output voltage This goal function yields the logic swing midpoint:
(Max(V(53))+Min(V(53)))/2
This gives us a mid-swing voltage at 1.25044 V
This goal function yields the low-to-high delay:
XatNthY(V(53),1.25044,19)- XatNthY(V(Vin1),1.25,19)
This gives tPLH = 0.611 ns.
This goal function yields the high-to-low delay:
XatNthY(V(53),1.25044,20)- XatNthY(V(Vin1),1.25,20)
This gives tPHL = 0.9814 ns.
From tPLH and tPHL we can find tP = 0.796 ns
Figure 7: Input and output voltage versus time for Gate 3 propagation delay measurements.
Area Calculation
We describe chip size as the sum of the individual MOSFET areas (W x L). The table below summarizes the calculation.
Table 4: Gate 3 Area Summary
|
# of gates
|
Type |
W(μm) |
L(μm) |
# of gates x A (μm2)
|
| 8 |
PFET |
0.25 |
0.25 |
0.5 |
| 8 |
NFET |
1 |
0.25 |
2 |
| 4 |
PFET |
8 |
0.25 |
8 |
| 4 |
NFET |
2 |
0.25 |
2 |
| 2 |
PFET |
4 |
0.25 |
2 |
| 2 |
NFET |
16 |
0.25 |
8 |
| 1 |
PFET |
32 |
0.25 |
8 |
| 1 |
NFET |
32 |
0.25 |
8 |
| Total |
|
|
|
38.5μm2 |
Figure of Merit
We define figure of merit as:
For this gate, the figure of merit equals:
FOM = (0.796 ns) x ( 1.126 mW) x (38.5 μm2) = 34.8 ns·mW·μm2
Design
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Optimized Gate Design
In designing the optimized gate, we consider both circuit structure and the figure of merit equation.
We first experiment with sizing FETs (adjusting W / L) progressively smaller as they near the output node within a gate. Sizing FETs like this considers the currents flowing to ground in a column of NFETs (NAND gate configuration). The output resides at the column top node. Each FET's parasitic capacitance stores some charge, and these capacitances discharge to ground when the output drops low. The top FET in the column carries the load discharge current and its own discharge current, whereas the bottom FET carries the discharge current of every FET above it plus the load current. Sizing FETs progressively can be important, since it minimizes bottlenecks in the current discharge path to ground. This should decrease the propagation delay, since the circuit can drop low faster with the improved current discharge path.[1] Unfortunately, in our simulations this fancy designing shows minimal improvements in propagation delay for all the given gates.
Since CMOS has minimal current flow into the gate (only a little flows in to charge parasitic capacitances), only the last element in the circuit (the driven element) contributes current to charge the load capacitance. Our simulations show that changes in the circuitry driving the final output stage affects the output characteristics minimally. Thus, we made the driving circuitry small and adjusted output element size. For gate 2, the two-level gate with 4 input NANDs, adding a buffer allows us to adjust only a small inverter, rather than the larger NOR gate. This helps keep chip area down and slightly increases the overall current sourcing and sinking ability for our small gate.
The figure of merit equation also shows a clear direction for circuit optimization. Decreasing W/L ratios decreases current conduction. This increases propagation delay, since an inverse relation exists between propagation delay and current input. Lower current also reduces power dissipation, since P = V∙I. Finally, we define chip area as the sum of W∙L products. Since channel length, L, remains constant at the minimum feature size, decreasing channel width, W, decreases area and power while increasing propagation delay. Lowering two FOM elements while increasing one seems like a fair trade, since we primarily care about our circuit's FOM.
Increasing propagation time means that output voltage may not swing rail-to-rail at some input frequencies, so we take care to maintain noise margins greater than 0.25V.
Optimized Gate Analysis
Power Measurements
Figure 8: Average power dissipation measurement for the Optimized Gate
We measure power dissipation at steady-state after at least 5 clock cycles. Gate power dissipation equals “power from the source (VDD∙IDD)” plus “power from the input (VIN∙IIN)” minus “power out (VOUT∙IOUT)”.
Plotting “AVGX( - W(Vdd) - W(Vin) - W(Cout), 10n)” and using cursors yields an average power dissipation PAV = 0.349 mW.
* Note: The negative signs come from pSpice sign convention. This does yield correct power values.
Speed Measurements
We define propagation delay as:
where tPLH and tPHL measure the low-to-high and high-to-low delays.
Figure 9: Input and output voltage versus time for the Optimized Gate propagation delay measurements
Low-to-high delay measures time between the output voltage midpoint and the input voltage midpoint when the output changes from the minimum to maximum value. We measure high-to-low when the output changes from the minimum to maximum value.
Decreasing W/L ratios slows the gate significantly, so propagation delay measurements require a lower input frequency. These measurements use 33.3 MHz for an input frequency.
Plotting VIN and VOUT versus time at this reduced frequency and using cursors yields:
VOH = 2.5V VOL = 0V
These values allow us to measure the propagation delays:
tPLH = 3.65 ns tPHL = 4.53 ns
These measurements yield:
tP = 4.09 ns
Area Calculation
We describe chip size as the sum of the individual MOSFET areas (W x L). The table below summarizes the calculation.
Table 5: Optimized Gate Area Summary
|
# of gates
|
Type |
W(μm) |
L(μm) |
# of gates x A (μm2)
|
| 11 |
PFET |
0.25 |
0.25 |
0.6875 |
| 11 |
NFET |
0.25 |
0.25 |
0.6875 |
| 1 |
PFET |
1.9 |
0.25 |
0.475 |
| 1 |
NFET |
0.6 |
0.25 |
0.15 |
| Total |
|
|
|
2 μm2 |
Noise Margins
Noise margins define the maximum disturbance a logic circuit can withstand without producing logic errors.
We define the high and low noise margins as:
Figure 10: Optimized Gate Voltage Transfer Characteristic (VTC) for measuring VIL and VIH
This plot shows the critical voltages VIL= 1.57V and VIH = 1.58V. We use these time-independent values to determine noise margins. Since 100 MHz input frequency does not allow the output voltage to swing rail-to-rail in one clock cycle, the VTC does not yield the operational values VOL and VOH.
In order to assure proper operation in all cases, we verify proper noise margins for the worst-case situations.
Figure 11: Optimized gate 2.5V to 0V response for measuring turn-on VOL and stable operation VOL and VOH values
Here, the output voltage starts high and must pull-down far enough in one half cycle (when the input stays low) to maintain NML > 0.25V. At the first minimum, we find an output voltage VOL = 1.14V, so the low noise margin NML = 0.43V. During stable operation VOL= 0.409V and VOH = 1.90V yielding NMH = 0.32V and NML = 1.16V.
Figure 12: Optimized gate 0V to 2.5V response for measuring turn-on VOH and stable operation VOL and VOH values
Here, the output voltage starts low and must pull-up far enough in one half cycle (when the input stays high) to maintain NMH > 0.25V. At the first maximum, we find an output voltage VOH = 1.83V, so the high noise margin NMH = 0.25V (this value actually stays slightly above 0.25V, so it meets the NMH > 0.25V requirement). During stable operation VOL= 1.00V and VOH = 2.35V yielding NMH = 0.77V and NML = 0.57V.
The low and high noise margins remain greater than 0.25V at all times. This verifies 100 MHz operation for the optimized gate.
Figure of Merit
We define figure of merit as:
For this gate, the figure of merit equals:
FOM = (1.25ns) x (0.708mW) x (13.5μm2) = 2.86 ns·mW·μm2
Appendix
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Description of Analysis Methods
Evaluate Goal Functions
PSpice Goal functions extract datapoints from traces and analog functions (functions one can plot in continuous time). We use the following goal functions and analog functions in this project:
YatX(X(t), T_eval) – This Goal Function gives the value 'X(t)' at time 'T_eval'.
XatNthY(X(t), Y_val, N) – This Goal function gives the time when 'X(t)' displays the value 'Y_val' for the Nth time over all measured time.
Min(X(t)) – This Goal Function gives the minimum value of 'X(t)'.
Max(X(t)) – This Goal Function gives the maximum value of 'X(t)'.
AVG(X(t)) – This Analog Function displays the running average of 'X(t)' over the entire range of datapoints.
AVGX(X(t),tau) – This Analog Function displays the running average of 'X(t)' starting at 'tau' up to the end of the range of datapoints.
Measure With Cursors
PSpice cursors allow the user to select points on a plot using the mouse cursor. The right and left mouse buttons control separate cursors (possibly on separate curves) allowing simultaneous measurements, and the cursor value window also displays the difference between the two cursor locations. All values not obtained with Goal functions in these simulations result from cursor measurements.
PSpice Code
Gate 1
In this simulation, we tie all inputs to a 2.5V square wave at 100 MHz. The rise and fall times for this square wave equal 0.5ns. 2.5V and 0V serve as the positive and negative rails. The transient analysis runs for 200ns, but only saves data after the first 100ns where the circuit remains stable. This gives data for 10 clock cycles. See Fig. A1, A2 for circuit diagrams with node numbers labeled. Note that nodes 1 through 8 connect to the node "Vin1". Click on the "show code" link below to view the code.
#
* Patrick Beck, Trevor McGuire, Michael Brust; Group 10; http://s02g10ee307w08.pbwiki.com/
* EE 307 CMOS AND Gate Project Winter 2008
* Base code supplied by Dr. Braun, modified by Group 10 W'08
* BIG AND Gate
Vdd Vdd 0 2.5
Vin Vin1 0 PULSE (0 2.5 0 0.5n 0.5n 5n 10n)
************************************************************
* Big Two-Level AND Gate Figures 1,4,7 *
* Big NAND Gate with all inputs (1-8) tied together *
************************************************************
MP1 Vdd Vin1 18 Vdd CMOSP W=0.25u L=0.25u
MP2 Vdd Vin1 18 Vdd CMOSP W=0.25u L=0.25u
MP3 Vdd Vin1 18 Vdd CMOSP W=0.25u L=0.25u
MP4 Vdd Vin1 18 Vdd CMOSP W=0.25u L=0.25u
MP5 Vdd Vin1 18 Vdd CMOSP W=0.25u L=0.25u
MP6 Vdd Vin1 18 Vdd CMOSP W=0.25u L=0.25u
MP7 Vdd Vin1 18 Vdd CMOSP W=0.25u L=0.25u
MP8 Vdd Vin1 18 Vdd CMOSP W=0.25u L=0.25u
MN8 18 Vin1 17 0 CMOSN W=16u L=0.25u
MN7 17 Vin1 16 0 CMOSN W=16u L=0.25u
MN6 16 Vin1 15 0 CMOSN W=16u L=0.25u
MN5 15 Vin1 14 0 CMOSN W=16u L=0.25u
MN4 14 Vin1 13 0 CMOSN W=16u L=0.25u
MN3 13 Vin1 12 0 CMOSN W=16u L=0.25u
MN2 12 Vin1 11 0 CMOSN W=16u L=0.25u
MN1 11 Vin1 0 0 CMOSN W=16u L=0.25u
* Inverting buffer to output
MP9 51 18 Vdd Vdd CMOSP W=4u L=0.25u
MN9 51 18 0 0 CMOSN W=4u L=0.25u
* Load Capacitance
Cout1 51 0 1p
*****************************************************************************
* FET Model Parameters *
* From http://www.mosis.org/Technical/Testdata/t14y_tsmc_025_level3.txt *
* TSMC (0.25 micron) DATE: Jun 11/01 LOT: T14Y WAF: 03 DIE: N_Area_Fring *
* DEV: N3740/10 * Temp= 27 *
*****************************************************************************
.MODEL CMOSN NMOS ( LEVEL = 3
+ TOX = 5.7E-9 NSUB = 1E17 GAMMA = 0.4317311
+ PHI = 0.7 VTO = 0.4238252 DELTA = 0
+ UO = 425.6466519 ETA = 0 THETA = 0.1754054
+ KP = 2.501048E-4 VMAX = 8.287851E4 KAPPA = 0.1686779
+ RSH = 4.062439E-3 NFS = 1E12 TPG = 1
+ XJ = 3E-7 LD = 3.162278E-11 WD = 1.232881E-8
+ CGDO = 6.2E-10 CGSO = 6.2E-10 CGBO = 1E-10
+ CJ = 1.81211E-3 PB = 0.5 MJ = 0.3282553
+ CJSW = 5.341337E-10 MJSW = 0.5 )
.MODEL CMOSP PMOS ( LEVEL = 3
+ TOX = 5.7E-9 NSUB = 1E17 GAMMA = 0.6348369
+ PHI = 0.7 VTO = -0.5536085 DELTA = 0
+ UO = 250 ETA = 0 THETA = 0.1573195
+ KP = 5.194153E-5 VMAX = 2.295325E5 KAPPA = 0.7448494
+ RSH = 30.0776952 NFS = 1E12 TPG = -1
+ XJ = 2E-7 LD = 9.968346E-13 WD = 5.475113E-9
+ CGDO = 6.66E-10 CGSO = 6.66E-10 CGBO = 1E-10
+ CJ = 1.893569E-3 PB = 0.9906013 MJ = 0.4664287
+ CJSW = 3.625544E-10 MJSW = 0.5 )
*****************************************************************************
.TRAN 20p 200n 100n 10p
.PROBE
.END
Gate 2
In this simulation, we tie all inputs to a 2.5V square wave at 100 MHz. The rise and fall times for this square wave equal 0.5ns. 2.5V and 0V serve as the positive and negative rails. The transient analysis runs for 100ns (10 clock cycles), displaying both turn-on response and stable operation. See Fig. A3, A4, A5 for circuit diagrams with node numbers labeled. Note that nodes 1 through 8 connect to the node "Vin1". Click on the "show code" link below to view the code.
#
* Patrick Beck, Trevor McGuire, Michael Brust; Group 10; http://s02g10ee307w08.pbwiki.com/
* EE 307 CMOS AND Gate Project Winter 2008
* Base code supplied by Dr. Braun, modified by Group 10 W'08*
* Medium Two-Level AND Gate
* Rails
Vdd Vdd 0 2.5
Vin Vin1 0 PULSE (0 2.5 0 0.5n 0.5n 5n 10n)
************************************************************
* Medium Two-Level AND Gate Figures 2,5 *
* All inputs (1-8) tied together *
************************************************************
Xupper Vin1 Vin1 Vin1 Vin1 Upper_out Vdd NAND4
Xlower Vin1 Vin1 Vin1 Vin1 Lower_out Vdd NAND4
Xnor Upper_out Lower_out 52 Vdd NOR2x4
Cout2 52 0 1p
************************************************************
* Subcircuit Definitions *
************************************************************
.SUBCKT NAND4 In1 In2 In3 In4 Out Vdd
MP1 Out In1 Vdd Vdd CMOSP W=0.25u L=0.25u
MP2 Out In2 Vdd Vdd CMOSP W=0.25u L=0.25u
MP3 Out In3 Vdd Vdd CMOSP W=0.25u L=0.25u
MP4 Out In4 Vdd Vdd CMOSP W=0.25u L=0.25u
MN4 Out In4 3 0 CMOSN W=4u L=0.25u
MN3 3 In3 2 0 CMOSN W=4u L=0.25u
MN2 2 In2 1 0 CMOSN W=4u L=0.25u
MN1 1 In1 0 0 CMOSN W=4u L=0.25u
.ENDS ; NAND4
.SUBCKT NOR2x4 In1 In2 Out Vdd
MP1 Out In1 1 Vdd CMOSP W=8u L=0.25u
MP2 1 In2 Vdd Vdd CMOSP W=8u L=0.25u
MN2 Out In2 0 0 CMOSN W=2u L=0.25u
MN1 Out In1 0 0 CMOSN W=2u L=0.25u
.ENDS ; NOR2x4
*****************************************************************************
* FET Model Parameters *
* From http://www.mosis.org/Technical/Testdata/t14y_tsmc_025_level3.txt *
* TSMC (0.25 micron) DATE: Jun 11/01 LOT: T14Y WAF: 03 DIE: N_Area_Fring *
* DEV: N3740/10 * Temp= 27 *
*****************************************************************************
.MODEL CMOSN NMOS ( LEVEL = 3
+ TOX = 5.7E-9 NSUB = 1E17 GAMMA = 0.4317311
+ PHI = 0.7 VTO = 0.4238252 DELTA = 0
+ UO = 425.6466519 ETA = 0 THETA = 0.1754054
+ KP = 2.501048E-4 VMAX = 8.287851E4 KAPPA = 0.1686779
+ RSH = 4.062439E-3 NFS = 1E12 TPG = 1
+ XJ = 3E-7 LD = 3.162278E-11 WD = 1.232881E-8
+ CGDO = 6.2E-10 CGSO = 6.2E-10 CGBO = 1E-10
+ CJ = 1.81211E-3 PB = 0.5 MJ = 0.3282553
+ CJSW = 5.341337E-10 MJSW = 0.5 )
.MODEL CMOSP PMOS ( LEVEL = 3
+ TOX = 5.7E-9 NSUB = 1E17 GAMMA = 0.6348369
+ PHI = 0.7 VTO = -0.5536085 DELTA = 0
+ UO = 250 ETA = 0 THETA = 0.1573195
+ KP = 5.194153E-5 VMAX = 2.295325E5 KAPPA = 0.7448494
+ RSH = 30.0776952 NFS = 1E12 TPG = -1
+ XJ = 2E-7 LD = 9.968346E-13 WD = 5.475113E-9
+ CGDO = 6.66E-10 CGSO = 6.66E-10 CGBO = 1E-10
+ CJ = 1.893569E-3 PB = 0.9906013 MJ = 0.4664287
+ CJSW = 3.625544E-10 MJSW = 0.5 )
*****************************************************************************
* Tests time dependent operation
.TRAN 20p 100n 0n 10p
* Sweeps DC input voltage for VTC measurements
*.DC Vin 0 2.5 0.001
.PROBE
.OP
.END
Gate 3
In this simulation, we tie all inputs to a 2.5V square wave at 100 MHz. The rise and fall times for this square wave equal 0.5ns. 2.5V and 0V serve as the positive and negative rails. The transient analysis runs for 200ns, displaying both the initial turn-on response and stable operation. See Fig. A6, A7, A8 for the circuit diagram with node numbers labeled. Note that nodes 1 through 8 connect to the node "Vin1". Click on the "show code" link below to view the code.
#
* Patrick Beck, Trevor McGuire, Michael Brust; Group 10; http://s02g10ee307w08.pbwiki.com/
* EE 307 CMOS AND Gate Project Winter 2008
* Base code supplied by Dr. Braun, modified by Group 10 W'08*
* Four-Level AND Gate
* Rails
Vdd Vdd 0 2.5
Vin Vin1 0 PULSE (0 2.5 0 0.5n 0.5n 5n 10n)
************************************************************
* Four-Level AND Gate Figures 3,6 *
* All inputs (1-8) tied together *
************************************************************
X1Nand Vin1 Vin1 X1Nand_out Vdd NAND2
X2Nand Vin1 Vin1 X2Nand_out Vdd NAND2
X3Nand Vin1 Vin1 X3Nand_out Vdd NAND2
X4Nand Vin1 Vin1 X4Nand_out Vdd NAND2
X1Nor X1Nand_out X2Nand_out X1Nor_out Vdd NOR2x4
X2Nor X3Nand_out X4Nand_out X2Nor_out Vdd NOR2x4
X1Nand2x16 X1Nor_out X2Nor_out NAND2_out Vdd NAND2x16
MP53 53 NAND2_out Vdd Vdd CMOSP W=32u L=0.25u
MN53 53 NAND2_out 0 0 CMOSN W=32u L=0.25u
Cout3 53 0 1p
************************************************************
* Subcircuit Definitions *
************************************************************
.SUBCKT NOR2x4 In1 In2 Out Vdd
MP1 Out In1 1 Vdd CMOSP W=8u L=0.25u
MP2 1 In2 Vdd Vdd CMOSP W=8u L=0.25u
MN2 Out In2 0 0 CMOSN W=2u L=0.25u
MN1 Out In1 0 0 CMOSN W=2u L=0.25u
.ENDS ; NOR2x4
.SUBCKT NAND2 In1 In2 Out Vdd
MP1 Out In1 Vdd Vdd CMOSP W=0.25u L=0.25u
MP2 Out In2 Vdd Vdd CMOSP W=0.25u L=0.25u
MN2 Out In2 1 0 CMOSN W=1.00u L=0.25u
MN1 1 In1 0 0 CMOSN W=1.00u L=0.25u
.ENDS ; NAND2
.SUBCKT NAND2x16 In1 In2 Out Vdd
MP1 Out In1 Vdd Vdd CMOSP W=4u L=0.25u
MP2 Out In2 Vdd Vdd CMOSP W=4u L=0.25u
MN2 Out In2 1 0 CMOSN W=16u L=0.25u
MN1 1 In1 0 0 CMOSN W=16u L=0.25u
.ENDS ; NAND2x16
*****************************************************************************
* FET Model Parameters *
* From http://www.mosis.org/Technical/Testdata/t14y_tsmc_025_level3.txt *
* TSMC (0.25 micron) DATE: Jun 11/01 LOT: T14Y WAF: 03 DIE: N_Area_Fring *
* DEV: N3740/10 * Temp= 27 *
*****************************************************************************
.MODEL CMOSN NMOS ( LEVEL = 3
+ TOX = 5.7E-9 NSUB = 1E17 GAMMA = 0.4317311
+ PHI = 0.7 VTO = 0.4238252 DELTA = 0
+ UO = 425.6466519 ETA = 0 THETA = 0.1754054
+ KP = 2.501048E-4 VMAX = 8.287851E4 KAPPA = 0.1686779
+ RSH = 4.062439E-3 NFS = 1E12 TPG = 1
+ XJ = 3E-7 LD = 3.162278E-11 WD = 1.232881E-8
+ CGDO = 6.2E-10 CGSO = 6.2E-10 CGBO = 1E-10
+ CJ = 1.81211E-3 PB = 0.5 MJ = 0.3282553
+ CJSW = 5.341337E-10 MJSW = 0.5 )
.MODEL CMOSP PMOS ( LEVEL = 3
+ TOX = 5.7E-9 NSUB = 1E17 GAMMA = 0.6348369
+ PHI = 0.7 VTO = -0.5536085 DELTA = 0
+ UO = 250 ETA = 0 THETA = 0.1573195
+ KP = 5.194153E-5 VMAX = 2.295325E5 KAPPA = 0.7448494
+ RSH = 30.0776952 NFS = 1E12 TPG = -1
+ XJ = 2E-7 LD = 9.968346E-13 WD = 5.475113E-9
+ CGDO = 6.66E-10 CGSO = 6.66E-10 CGBO = 1E-10
+ CJ = 1.893569E-3 PB = 0.9906013 MJ = 0.4664287
+ CJSW = 3.625544E-10 MJSW = 0.5 )
*****************************************************************************
.TRAN 20p 200n 0n 10p
.PROBE
.END
Optimized Gate
In this simulation, we tie all inputs to a 2.5V square wave (individual input waves described in the code). The rise and fall times for these square waves equal 0.5ns. 2.5V and 0V serve as the positive and negative rails. The transient analysis runs for 100ns, diplaying both turn-on response and stable operation. A DC sweep measures the VTC to check noise margins for thsi gate. See Fig. A9, A10, A11, A12 for the circuit diagrams with node numbers labeled. Note that nodes 1 through 8 connect to the node "Vin1". Click on the "show code" link below to view the code.
#
* Patrick Beck, Trevor McGuire, Michael Brust; Group 10; http://s02g10ee307w08.pbwiki.com/
* EE 307 CMOS AND Gate Project Winter 2008
* Base code supplied by Dr. Braun, modified by Group 10 W'08
* Medium Two-Level AND Gate (Modified)
* Rails
Vdd Vdd 0 2.5
* Tests standard operation at 100 MHz and checks maximum pull-up strength
Vin Vin1 0 PULSE (0 2.5 0 0.5n 0.5n 5n 10n)
* Tests standard operation at 100 MHz and checks maximum pull-down strength
*Vin Vin1 0 PULSE (2.5 0 0 0.5n 0.5n 5n 10n)
* Tests operation at 33.3 MHz to show rail-to-rail transitions and allow for propagation delay measurements.
*Vin Vin1 0 PULSE (0 2.5 0 0.5n 0.5n 15n 30n)
************************************************************
* Medium Two-Level AND Gate Figures 2,5 *
* All inputs (1-8) tied together *
************************************************************
Xupper Vin1 Vin1 Vin1 Vin1 Upper_out Vdd NAND4
Xlower Vin1 Vin1 Vin1 Vin1 Lower_out Vdd NAND4
Xnor Upper_out Lower_out 52 Vdd NOR2x4
************************************************************
* Additional CMOS inverters as output buffers *
************************************************************
MP1 53 52 Vdd Vdd CMOSP W=0.25u L=0.25u
MN1 53 52 0 0 CMOSN W=0.25u L=0.25u
MP2 54 53 Vdd Vdd CMOSP W=1.9u L=0.25u
MN2 54 53 0 0 CMOSN W=0.6u L=0.25u
Cout2 54 0 1p
************************************************************
* Subcircuit Definitions *
************************************************************
.SUBCKT NAND4 In1 In2 In3 In4 Out Vdd
MP1 Out In1 Vdd Vdd CMOSP W=0.25u L=0.25u
MP2 Out In2 Vdd Vdd CMOSP W=0.25u L=0.25u
MP3 Out In3 Vdd Vdd CMOSP W=0.25u L=0.25u
MP4 Out In4 Vdd Vdd CMOSP W=0.25u L=0.25u
MN4 Out In4 3 0 CMOSN W=0.25u L=0.25u
MN3 3 In3 2 0 CMOSN W=0.25u L=0.25u
MN2 2 In2 1 0 CMOSN W=0.25u L=0.25u
MN1 1 In1 0 0 CMOSN W=0.25u L=0.25u
.ENDS ; NAND4
.SUBCKT NOR2x4 In1 In2 Out Vdd
MP1 Out In1 1 Vdd CMOSP W=0.25u L=0.25u
MP2 1 In2 Vdd Vdd CMOSP W=0.25u L=0.25u
MN2 Out In2 0 0 CMOSN W=0.25u L=0.25u
MN1 Out In1 0 0 CMOSN W=0.25u L=0.25u
.ENDS ; NOR2x4
*****************************************************************************
* FET Model Parameters *
* From http://www.mosis.org/Technical/Testdata/t14y_tsmc_025_level3.txt *
* TSMC (0.25 micron) DATE: Jun 11/01 LOT: T14Y WAF: 03 DIE: N_Area_Fring *
* DEV: N3740/10 * Temp= 27 *
*****************************************************************************
.MODEL CMOSN NMOS ( LEVEL = 3
+ TOX = 5.7E-9 NSUB = 1E17 GAMMA = 0.4317311
+ PHI = 0.7 VTO = 0.4238252 DELTA = 0
+ UO = 425.6466519 ETA = 0 THETA = 0.1754054
+ KP = 2.501048E-4 VMAX = 8.287851E4 KAPPA = 0.1686779
+ RSH = 4.062439E-3 NFS = 1E12 TPG = 1
+ XJ = 3E-7 LD = 3.162278E-11 WD = 1.232881E-8
+ CGDO = 6.2E-10 CGSO = 6.2E-10 CGBO = 1E-10
+ CJ = 1.81211E-3 PB = 0.5 MJ = 0.3282553
+ CJSW = 5.341337E-10 MJSW = 0.5 )
.MODEL CMOSP PMOS ( LEVEL = 3
+ TOX = 5.7E-9 NSUB = 1E17 GAMMA = 0.6348369
+ PHI = 0.7 VTO = -0.5536085 DELTA = 0
+ UO = 250 ETA = 0 THETA = 0.1573195
+ KP = 5.194153E-5 VMAX = 2.295325E5 KAPPA = 0.7448494
+ RSH = 30.0776952 NFS = 1E12 TPG = -1
+ XJ = 2E-7 LD = 9.968346E-13 WD = 5.475113E-9
+ CGDO = 6.66E-10 CGSO = 6.66E-10 CGBO = 1E-10
+ CJ = 1.893569E-3 PB = 0.9906013 MJ = 0.4664287
+ CJSW = 3.625544E-10 MJSW = 0.5 )
*****************************************************************************
* Tests time dependent operation
.TRAN 20p 100n 0n 10p
* Sweeps DC input voltage for VTC measurements
*.DC Vin 0 2.5 0.001
.PROBE
.OP
.END
Figures
Gate 1
Figure A1: Gate 1 functional diagram with external node numbers
|
Figure A2: Gate 1 circuit diagram with all node numbers
|
Gate 2
Figure A3: Gate 2 functional diagram with external node numbers
|
Figure A4: NAND4 with subcircuit node numbers
|
Figure A5: NOR2x4 with subcircuit node numbers
|
Gate 3
Figure A6: Gate 3 functional diagram with external node numbers (simple CMOS inverter on output)
|
Figure A7: NAND2 / NAND2x16 with subcircuit node numbers (W / L ratios vary between the two gate. See code above for details)
|
Figure A8: NOR2x4 with subcircuit node numbers
|
Optimized Gate
Figure A9: Gate 3 functional diagram with external node numbers (inverters described in fig. A11)
|
Figure A10: NAND4 with subcircuit node numbers & W / L ratios
|
Figure A11: CMOS inverters as an ouput buffer with node numbers & W / L ratios
|
Figure A12: NOR2x4 with subcircuit node numbers & W / L ratios
|
References
[top]
1. Mary Jane Irwin & Vijay Narayanan, CSE477 VLSI Digital Circuits Fall 2003, Lecture Slides, [Online]. Available: http://mdlwiki.cse.psu.edu/twiki/pub/MDL/MJI477/cse477-11speed.ppt, Slides 15, 18-20 [Accessed: February 25, 2007]
Adapted from J. Rabaey, A. Chandrakasan, & B. Nikolic, Digital Integrated Circuits, Second Ed., 2003, Prentice Hall.
2. K. Gopalan, Introduction to Digital Microelectronic Circuits. Chicago: Irwin, 1996, p. 10-13, 16, 373-384, 392-400.
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